This lecture aims the conception of elementary digital cells pointing out the strong links between electrical static parameters and dynamic parameters with the physical parameters related to semiconductor processing used for integrated circuit fabrication of last CMOS nodes (from gate-length Lg= 0.5µm under supply voltage Vdd= 5V to 22nm under 0.85V).
At the end of this course, the students will know how to determine the main parameters involved in DC performances for CMOS nodes (VT, IOn, IOff, Gm, Gd, Pdc) in addition to dynamique operation (Pac, Fac, tau_n, tau_p, Cload). They will know how to realize single logic functions using CMOS technologies (NAND, NOR, XOR, NO, Ring oscillators ) with help of corresponding schematics . Reinforcement is done on scaling effects onto electrical parameters for N-channel and P-channel transistors, the build-up of any logic functions with CMOS gates and how to use the main parameters given by SPICE models 1-3, in order to obtain electrical characteristics from these devices to the digital cells.

Chapter 1 – PART A : Conception of Digital Circuits

1. General introduction to technology scaling and production of IC’s, scenario from silicon bulk (1960) to the last generations with FinFETs and Gate-All-Around (GAA), Carbon nanotubes (CNT).
2. Different families of devices and application types depending of speed and consumption
3. Principle of CMOS operation: from single gate to complex functionalities, voltage operation distinction between N-channel and P-channel devices
4. The different trends of microelectronics, SiGe, Strained Si, Double gate and FinFET, MEM’s, organic and molecular electronics towards nanoelectronics

Chapter 1 – PART B : Resistivity and Doping

1. Resistance and resistivity, Resistance per square, first design of integrated resistor
2. Diffused resistance, contacts and interconnections, influence of the doping
3. High integrated resistance and resistance calculation for any resistance shape
4. Measure of resistivity – 4 probe measurements
5. Conclusions

Chapter 2 : MOS (Métal-Oxide-Semiconductor) CAPACITANCE

1. Introduction to the MOS capacitance structure and its uses for CCD, EEPROM and MOSFETs
2. Basics on band diagrams build-up of the MOS structure: different regions of operations, influences of the gate type, flat-band voltage, the effects of main defects (interface traps and oxide charges)
3. Calculation of carrier concentrations (majority/minority carriers): simplified model
4. Theoretical electrostatics calculation: charge conservation, Poisson equation, electric field and space charge region extension
5. C – V Measurements: basic principle, frequency dependence and influence of main defects on the electrical characteristics
6. Summary of main C-V parameters with scaling dimensions

Chapter 3 : MOSFET Transistors used for Digital Applications

1. The MOSFETs
   The transistor architecture and layout
   o Operating regimes as a function of voltage conditions
   o Different types of MOSFET as a function of gate, channel types and threshold voltage
2. Region of operation and I-V characteristics as a function of VGS, VDS
   o From linear mode to saturation mode (SPICE Lev.1)
   o IDS current at any VDS : Memelinck techniques, analytical and graphical resolutions, influence of back bias VB (REV vs. FWD), effect of transistor type NMOS vs. PMOS
3. Extraction of the basic transistor parameters
   o Transistor gains: transconductance, conductance and bulk transconductance, small signal analysis (1st modeling without capacitances)
   o Sub-VT Ids-Vgs characteristics, effect of VDS and LG on IOff by Drain Induced Barrier Lowering (DIBL)
   o Threshold voltage VT extraction and influence of the doping profile, Short Channel Effect (SCE) and Narrow Channel Effect (NCE), effective channel length and width
   o Mobility Reduction with vertical field (SPICE Lev.1), 1st modeling with Gm extraction
   Conclusions

Chapter 4 : The BASIC GATES

1. The CMOS digital logic inverter – Goals
   o Generalities on Voltage Transfer Characteristics (VTC): Golden rules and definition of threshold voltage for logic input/output operation (VIH, VOH, VIL, VOL)
   o Noise margins
2. Different inverter types: VTC analysis, layout, analytical and graphical descriptions (Memelinck Technique)
   o Passive load
   o Saturated load
   o Depletion load
   o Speudo NMOS and dynamic load with CMOS inverters
3. Conclusions

Chapter 5 : The Digital Model: From Static Logic Gates to Dynamic operation

1. The Digital Model
   • Goals and first approach :
   • Resistive effects
   • Capacitance effects
   • Small signal modeling
   • temporal parameters
2. Dynamic characteristics:
   • Inverter capacitance
   • Propagation time,
   • Factor of merit
   • 2 coupled inverters modeling and layout,
   • Chain of inverter gates, ring oscillators (ROs) and buffer optimization
3. Principle of CMOS gates and their switching voltage condition:
   • NAND gates
   • NOR gates
   • XOR and XNOR gates
   • Application to any logic functions
4. Summary and Final conclusions: What you have learnt in this course…
   Prospects