IPCEI Nano 2022

R&D activities

Start date

End date

Overall project cost

Description

The nano 2022 project is in the continuity of nano 2017, but the research axes of Yncréa Méditerranée are to establish the reliability of CMOS 28FD-P28 and BiCMOS technologies for digital, mixed and medium power applications (smart power) in order to obtain solutions to gain resistance to aging.

These improvements are realized by hot/cold carriers, high temperature, high frequency performance, high and low voltage supply (HV/LV), low power (LP) as well as for medium power AMS and analog circuits (radio frequency mode).

Objectifs

The objective of Yncréa Méditerranée is to optimize new digital integrated circuits in CMOS and BiCMOS technologies. The circuits and devices tested are dedicated to low power digital applications (LP) with supply voltage 0.65 to 1 V and medium power applications with supply voltage 6V to 20 V in RF mode. The study is based on innovations from 28nm to 22nm FDSOI nodes (metal gate and high K dielectrics) with ultra thin (core) and thick (IO) dielectrics as well as on conventional silicon substrate (CMOS 40nm to 28nm LP) and extended drain EDMOS or LDMOS (0.5µm to 1µm). The objective is to guarantee the lifetime of the devices in spite of the increase of the constraints in temperature and the variability of the electrical responses for the various profiles of missions according to the quality of the processes, according to the types of applications and the interaction of the mechanisms of degradation (aging) in use. The second axis is the extension of LP and smart power applications to adaptive and/or compensating solutions to gain lifetime of mixed circuits used for analog applications for ST markets such as automotive, space, avionics and IoT.

Main partner of the project

Partners

CEA LETI, ADIXEN, CEA LIST, CEMES, CMP-GC, EXCICO-LASSE, IBM, ICCF, IEMN, III-V lab, IM2NP, IMS, INRIA, Institut d'Optique, LAAS, Lab STICC, Magillem, Paris TECH, Université Nice Sophia, UPS-IEF-Paris Sud

More details

Description des travaux :

Area 1: Expanding applications for 28nm FDSOI - C40 (bulk silicon)

The reliability of FDSOI and M40 technologies is to be determined as a function of the different sources of variabilityto to (local and global) and the temporal variability that translates into increased device and cell degradation with temperature, power supply voltage boosts (VDD to VDDmax) for cores and IOs. The aim is to quantify the greatest reductions in lifetime as a function of technology nodes, operating voltage VDD and maximum drops in actual use VDDmax, depending on the design in nominalLG (WG) length (and width) and the nature (HKMG, SiON, SiO2) and thickness (Tox ) of the gate dielectric (architecture, spacer quality, access resistance). This will be done for this axis according to the types of applications and mission profiles (Automotive, Space, Avionics and IoT), i.e. for the low-voltage LV (GO1: VDD= 0.65V to 1V) and high-voltage HV (GO2: VDD= 3.3 to 4.8 V) ranges typical of ULP to LP applications. Solutions will be proposed at all design levels to improve predictive models of accelerated degradation based on degradation mechanisms and permanent/recoverable degradation over operating cycles. Another important topic will be to find possible solutions for reducing, compensating or adapting devices and circuits, with the aim of extending their lifetime for both types of use in digital operation for CMOS 28nm FDSOI (28FD or P28) and bulk silicon 100nm (C40-i140) technologies.

The main steps in this area are to develop studies on :

(1) Determining the lifetime of elementary devices and circuits between low voltage and maximum operating voltage (VDDmax) and determining the impact on operating margins as a function of structures and geometries and architecture (design and layout).

(2) modeling the interaction of degradation mechanisms between the different HC hot carrier modes (DC-AC) with BTI temperature degradation, and the relaxation domains (HC + BTI) between low and high voltage in logic cores and input-output (IO) devices.

(3) the interaction of degradation mechanisms (HC, BTI) with natural irradiations as a function of doses, this point being able to determine the possible influence of self-heating as a function of geometries and architectures for thermal aspects.

The goal of this axis is to establish a precise modeling that allows to distinguish the worst case mechanisms of LV-HV degradation and the ratio of permanent vs.recoverable degradation specific to the operation of the different families of devices in real use (AC-DC) according to their geometry, architecture and process, and the impact in the medium and long term on the lifetime of the elementary circuits with the increase of the environmental constraints in temperature and under natural irradiations 

Area 2: Reliability of BiCMOS technologies (N- and P- EDMOS)

The objective of this axis is to obtain the sensitivity to aging and breakdown of devices subjected to hot carriers and high temperature, as well as to voltage drops for mixed CMOS and BiCMOS devices and circuits, i.e. for a wide temperature range (80-150°C). This is aimed at the reliability of different types of applications (Automotive, Avionics, IoT) up to the medium power range (smart power) for mixed and analog applications that require a high level of stability, dedicated to a safe operation according to ISO 26262. The influence of topologies and dimensioning as well as the effect of variability are paramount for mixed-signal circuits. This will require quantifying the dispersion of frequency responses and nominal parameters at the transistor and cell level, which is dependent on the process quality (to) but also on the temporal variability due to HC and NBTI degradation (PBTI) and self-heating (SH), possibly involved up to the breakdown of source and drain dielectrics and junctions, which are intrinsically dependent on the bias cycles under DC acceleration and AC voltage drops

(1) Study of degradation in high voltage (VDD = 6 to 10 V) N- and P- EDMOS devices in order to precisely decorrelate the effects of the different mechanisms (DNIT interface states, DNot trapping, DNot deprotection) and the type of faults (permanent vs. recoverable) on the different parameters related to the analog performance (ION/IOff, Gm/IDS(Lin-Sat), Gd(Lin-Sat),So,Av,Rout, PIn/POut)

(2) Modeling of degradation in On and Off mode and as a function of N- and P- EDMOS structures (LWell/Leff,LSpacer, Lovlp, Lcontact) Fig.A1 and their nominal geometry (LG, WG), including the effects of voltage (VDD to VDDmax) and temperature at the transistor and cell level, down to the elementary circuits (cascode assembly, differential amplification, low noise). Consideration oftoetvariability due to aging as a function of operating modes.

(3) Determination of the degradation and sensitivity of analog mode devices by 1/f noise and RTN measurements on small geometries for the determination of the trap density, their frequency response and their impact in terms of signal-to-noise.

Fig.A1: Schematic of the structure of N-EDMOS transistors used for medium power applications with an extended drain zone (NDrift zone), an accumulation zone on N-well in series with the N-channel on Pl-well. The thickness of the gate oxide (SiO2) is Tox= 2.3nm (GO1) and 8.5nm (GO2) [4]. (b ) Lifetime plots between different N-channel MOSFETs (H5-H6) and EDMOS 0.5µm technologies in agreement with the high-energy hot carrier degradation mode between the standard CMOS Si-bulk: (¨) LG= 0.5µm, Tox= 12nm, VDD= 5V, ()LG= 0.35µm, Tox= 7nm, VDD= 3.3V compared to EDMOS technology withLG=0.5µm, VDD= 6V: (▲) GO1 and (▲) GO2 N channel. The measurement criterion is 10% reduction of the linear current IDlin(Vdm, Vgm) [4].

Results obtained

This study started on the performance and robustness study of the high voltage (HV) technology dedicated to RF applications by determining the worst-case voltage conditions of the onset of hot carrier (HC) degradation in N-channel extended drian transistors (EDMOS) of lengthLG= 0.5µm initially manufactured for a supply voltage VDD= 10V. This technology is manufactured with an ultra thin gate dielectric for the cores (2.3nm) and a thick oxide (8.5nm) for the IO devices. Optimization in performance and thermal effect forced to reduce the operating voltages to VDDmax= 6.6V operation (VDDnom= 6V) and to use a limited range between VGS and VGmax = 1.32V and 4.8V respectively. We have shown that HBD is a sensitive criterion for these switch and power technologies, starting from the Off mode (VGS= 0) towards the hot carrier regime (pulsed VG) in the low VGS stress ranges, especially in these 2.3nm thick SiO2 gate oxides where the electric field is strong enough to generate a hot hole injection peak from the gate-drain overlap region that extends to the gate, above the channel, from the drift region. The HC results showed a strong series resistance increase (RON) effect that results from a combined effect of hot hole trapping in the gate oxide (and passivation) and the increase of interface states (DNIT) that take the dominant role at long stress times, masking in the long run the effect of hole trapping that leads to a reduction of the effective channel length (at short stress times). We have shown that this involvement of hot holes could lead to the breakdown of the dielectric under hot carrier mode (HC) and to the loss of the device's functionality, as soon as the voltages VGS=VTH and VGmax are reached, which weakens the structure of the transistors, even with an extended drain that deflects the lateral electric field peak outside the channel.

Using the conditions for hole injection in the HC progressive mode, we obtained the acceleration laws in electric field and set an anticipation criterion for the detection of the frank breakdown and the determination of the duration of the N channel EDMOS transistors. We have shown that the same acceleration factor is obtained between the On and Off modes, this time as a function of a power law proportional to (VGS-VDS). This highlights the voltage safety domains for predicting the effective AC mode lifetime deduced from quasi-static calculations for signal shapes in RF and switch applications. Thus, the quasi-static calculations performed in conjunction with the ELDO simulations, are based on a 1% variation in RON resistivity to prevent breakdown for class E (and class A) operation for RF amplifiers operating at 1.8GHz. Similarly, using the degradation rate and aging function based on the set of mechanisms involved in the NEDMOS, allows to apply this technique to any signal shape and to compare with the experimental AC results which are first performed at low frequency.

In 2020, we completed the acquisition of new equipment (B1525, B1530) on the B1500 analyzer to set up a new experimental bench(Fig.A2) to test high voltage RF circuits (smart power) of EDMOS-LDMOS technology both on wafer and in package. We studied the reliability of N- and P- LDMOS technology. The development of new measurement techniques on the new bench will allow to link fast measurement phases (LP technology) and low (C40-28FD - 22FD) or high voltage stress (H9A).

Fig.A2 : Karl Susse 300mm electrical characterization bench in WGFMU (Waveform Generator Fast Measurement Unit) configuration on 28FD technology.

We have finalized the assembly of the experimental bench (B1525, B1530) on the 300 mm prober to swap the high/low voltage and DC/AC stress types for the 40LP-28LP and H9A technologies which allows us to develop a wide range of stress types and measurements (ultra fast measurements) to validate the lifetime and analyze the interaction of the AC-DC fault generation mechanisms according to the structures and topologies (process) of these technologies.

Publications over the period

The results of the first two years of the nano 2022 project have led to publications at the major international IEEE conferences at IRPS, ESREF as well as articles in the journal Microelectronics Reliability. They mainly focused on the reliability of EDMOS - LDMOS technologies for smart-power applications.

Newspapers

[1.] Li S., Bravaix A., Kussener E., Ney D., Federspiel X., Cacho F., "Hot-Carrier Degradation in P- and N- Channel EDMOS for Smart Power Application," Microelectronics Reliability, Vol. 114, pp. 113811-6, 2020.
Doi.org /10.1016/j.microrel.2020.113811

[2] Garba-Seybou T., Bravaix A., Federspiel X., , Cacho F., "Modeling HCD interaction between On and Off modes for 28nm FDSOI used for AC RF applications", Microelectronics Reliability, Vol. 126, pp. 114342, 1-6, 2021.
doi : 10.1016/j.microrel.2021.114342

IEEE International Conferences

[3.] Diouf C., Guitard N., Rafik M., Federspiel X., Bravaix A., Martinez J. J., Muller D., Roy D., "Process optimization for HCI improvement in I/O analog devices," in IEEE International Reliability Physics Symposium, (IRPS), 3B.1-1, 3B.1-6, 2019.
Doi: 10.1109/IRPS.2019.8720544

[Bravaix A., Kussener E., Ney D., Federspiel X., Cacho F., "Hot-Carrier induced Breakdown events fromOff to On mode in NEDMOS", in IEEE International Reliability Physics Symposium, (IRPS), 3A4-1, 3A4-6, 2020.
Doi: 10.1109/IRPS45951.2020.9129214

[5.] Li S., Bravaix A., Kussener E., Ney D., Federspiel X., Cacho F., "Hot-Carrier Degradation in P- and N- Channel EDMOS for Smart Power Application," 31st European Symposium Reliability on Electron Devices, Failure Physics and Analysis (ESREF) Conf., pp. 1-6, 2020.
Doi.org/10.1016/j.microrel.2020.113811

[6] Garba Seybou T., Federspiel X., Bravaix A., Cacho F., "Analysis of the interactions of HCD under "On" and "Off" state modes for 28nm FDSOI AC RF modelling", in IEEE International Reliability Physics Symposium, (IRPS), P31-1-6, 2021.
Doi: 10.1109/IRPS46558.2021.9405214

[Garba-Seybou T., Federspiel X., A. Bravaix, Cacho F., "Modeling HCD interaction between On and Off modes for 28nm FDSOI used for AC RF applications", in 32th European Symposium Reliability on Electron Devices, Failure Physics and Analysis (ESREF) Conf., pp. 1-6, 2021.
Doi: 10.1016/j.microrel.2021.114342

[8] Garba-Seybou T., Federspiel X., Bravaix A., Cacho F., "New Modelling Off-state TDDB for 130nm to 28nm CMOS nodes", to be published in IEEE International Reliability Physics Symposium, (IRPS), pp1-8, 2022.
Doi (to come)