Description
Microelectronics is a sector in which technological progress is very rapid, with the development of ever more integrated technologies every 18 to 24 months, leading to the arrival on the market of new generations of products every six months, and a continuous fall in production costs. The successive stages of this evolution are referred to as "technology nodes" and designated by their characteristic dimension, i.e. currently 32/28nm in industrialization and option development, 22/20nm in industrial R&D, 10nm in the advanced research phase with the first studies of 7 and 5nm in fundamental laboratories.
Two technologies currently enable us to go beyond 28nm: FinFET technology, originating from Darpa laboratories in the USA, first industrialized by Intel (from 22nm) and then by TSMC up to 14nm, and FDSOI ("Fully Depleted Silicon On Insulator") technology, whose performance and potential to replace CMOS transistors on bulk substrates (Si-Bulk) for the 28nm technology node were demonstrated as part of the ISDA alliance with IBM and the Nano 2012 project, and whose development beyond 28nm is at the heart of the Nano 2017 program. Nano 2017 aims to reposition FDSOI technology as an alternative to FinFET technology on the world market, with ST Microelectronics representing the main market leader.
Objectifs
ISEN has participated in the development of test procedures for advanced digital circuits for the advanced optimization of performance and reliability of these latest CMOS dies in the laboratory of ISEN-Toulon, on the electrical characterization bench (Prober Karl Susse 300mm). This allowed to establish their robustness to accelerated aging by developing new models of duration for these devices and elementary circuits under carrier mechanism (HC), at high temperature (BTI) and on their sensitivity to soft and hard breakdown (Breakdown). The comparison was made between M40 and 28nm CMOS nodes on bulk silicon and 28nm-22nm FDSOI which featured new metal/High-K/SiON gate stacking processes on UTBB (Ultra Thin Bulk Biased) with ground plane (dual gate backside control) and source/drain multidiffusion.
Main partner of the project
Partners
CEA LETI, ADIXEN, CEA LIST, CEMES, CMP-GC, EXCICO-LASSE, IBM, ICCF, IEMN, III-V lab, IM2NP, IMS, INRIA, Institut d'Optique, LAAS, Lab STICC, Magillem, Paris TECH, Université Nice Sophia, UPS-IEF-Paris Sud
Main teacher-researchers involved
Project Director
Alain BRAVAIX
Activity manager
Doctoral students :
- Marine Saliva (CIFRE ST Crolles)
- Damien Angot (CIFRE St Crolles)
- Cheikh Ndiaye (CIFRE ST Crolles)
- Wafa Arfaoui (CIFRE ST Crolles)
More details
The first part of the project consisted in determining the process influence of the 28nm FDSOI (HKMG gate) and M40 (PolySi/SiON gate) technologies on bulk silicon on the main intrinsic degradation mechanisms which are BTI, HC, SBD and HBD. This allowed us to obtain the first sets of parameters involved in the temporal modeling of their effective impact for low power and high speed applications of these digital technologies. In a second step, we have planned the specification of test boards to test boxed circuits composed of different types of cells and circuits in these technologies.
The second part allowed the development of real time tests based on mission profiles characteristic of automotive applications for the analysis of performance reduction under controlled environment for the 28nm FDSOI technology(Fig.A1). Initially, boards architected around ST's microcontroller and FPGAs were to allow real-time testing at high temperature (HTOL) of ST's technology. However, since the processors were not released at tape-out time during the project, we stayed at wafer-level on transistors, cells and elementary circuits, in order to modify the aging models according to the technological parameters (LP28 vs. 28FD) and to compare them to the dynamic results for the worst-case degradation in realistic operation, according to the different mission profiles. The same methodology has been applied to M40 type circuits made of 1.7nm thick SiON gate dielectric to determine the impact on lifetime.
The third part validated the methodology for the high performance FDSOI 28nm and low power M40 technologies between the degradation models, but at the level of transistors to elementary circuits, such as ring oscillators, NAND and NOR inverting logic gates in relation to the simulation results (RTL, Ring Oscillators, logic gates) We have determined the real time effects of BTI, HC or soft breakdown mechanisms as well as the importance of relaxation effects due to the recoverable part of the defects generated in these thin gate oxides. The study in dynamic regime gave rise to specific tests on cells as a function of the number of gates and frequency dependencies as a function of the shape of the signals, thus of the number of stressful periods(Fig.A2) seen by the devices, and in particular in terms of the proportion of permanent defects to recoverable defects as a function of the shape of the signals.
Fig.A1 : (a ) Structure of a CMOS cell of 28FD technology with the range of use of the bulk voltage (boy bias) in direct and inverse mode. (b) Evolution of the different contributions in DC and AC power of this technology between room temperature and high temperatures (125°C).
Results obtained
This study concerned aging tests performed on the 28FD CMOS die on devices of length LG= 38nm to 20nm (WG= 1 to 10μm) [1, 2]. The focus was on wearout modes strongly accelerated at room temperature, such as hot carrier (HC) degradation, and strongly activated at high Negative Bias Temperature (NBT). The worst case bias dependencies for the last processes that underwent the RTO (and RTA spike annealing) steps were used under DC stresses, and then the comparison to AC stresses allowed to establish on cells the effects of operating frequency, activity, duty cycle in the inverter and buffer chains (Fig.A2). Particular attention has been paid to the effect of the substrate voltage VB in reverse and forward bias (RBB and FBB) for characterization and stress modes [3, 4], given its use for self-adaptive circuits in dynamic mode (D-ABB) [5-9] for the development of the monitor-dependent methodology (PVTA) [10]. A technique for extracting and modeling the VB-FBB voltage value, required for HC and NBT degradation compensation, was developed based on the monitoring of current characteristics and the application of the body effect (strict linearities of dVTh and dIDS as a function of VB) that allow calculation and comparison with the experimental extraction [8]. Thus, we were able to obtain the values of VB necessary to neutralize HC degradation (as NBT), once the characteristics obtained before and after stress (for the considered temperatures) leading to a healing technique applied to the FDSOI nanoscale technology (28-20 nm) [2, 9].
Fig.A2: (a ) DDelay per gate of an inverter chain stressed at 125°C for VDD= 1.8V and for different operating frequencies, compared to DC stress (FDSOI HKMG,LG= 30nm, WN/WP = 0.4µm/0.6µm). (b) Shift in operating frequency for four types of digital cells based on inverters, multiplexers, NAND and NOR gates stressed under AC and DC conditions at 125°C. [8]
Publications over the period
The results have been valorized by publications at international IEEE conferences at IRPS, ESREF, IIRW, IOLTS as well as articles in the journal Microelectronics Reliability. They mainly focused on the adaptation of the HC and BTI degradation models by distinguishing the interaction between the mechanisms, as well as the possibility of total or partial recovery with the neutralization of a type of defects in the transistors (electron/hole injections from drain to gate) and the effect of the substrate voltage in direct mode (FWD) for compensation by sensing effect.
Newspapers
[1.] C. Ndiaye, V. Huard, X. Federspiel, F. Cacho, A. Bravaix, "Performance vs. Reliability Adaptive Body Bias Scheme in 28nm & 14nm UTBB FDSOI nodes," Microelectronics Reliab., Vol.64, pp. 158-162, Sept. 2016.
. doi.org /10.1016/j.microrel.2016.07.085
[2.] A . Bravaix, , F. Cacho, X. Federspiel, C. Ndiaye, S. Mhira, V. Huard, "Potentiality of Healing Techniques in Hot-Carrier Damaged 28nm FDSOI CMOS nodes", Microelectronics Reliab., Vol.64, pp.163-167, Sept. 2016.
doi.org /10.1016/j.microrel.2016.07.092
[3.] C . Ndiaye, V. Huard, X. Federspiel, F. Cacho, A. Bravaix, "Performance vs. Reliability Adaptive Body Bias Scheme in 28nm & 14nm UTBB FDSOI nodes", Microelectronics Reliab., Vol.64, pp. 158-162, Sept. 2016.
. doi.org /10.1016/j.microrel.2016.07.085
IEEE International Conferences
[4] Angot D., Huard V., Quoirin M., Federspiel X., Haendler S., Saliva M., Bravaix A., "The impact of high Vth drifts tail and real workloads on SRAM reliability", IEEE Int. Reliability Phys. Symp. at CA.10.1 - CA10-6, 2014.
Doi: 10.1109/IRPS.2014.6861126
[5.] Arfaoui W.; Federspiel X.; Bravaix A.; Mora P.; Cros A.; Roy D., "Application of compact HCI model to prediction of process effect in 28FDSOI technology," IEEE International Integrated Reliability Workshop Final Report (IIRW), pp. 69-72, 2014.
Doi: 10.1109/IIRW.2014.7049513
[6] Arfaoui W., Federspiel X.; Mora P.; Monsieur F.; Cacho F.; Roy D.; Bravaix A., "Energy-driven Hot-Carrier model in advanced nodes", IEEE Int. Reliability Phys. Symp., XT.12.1 - XT.12.5, 2014.
Doi: 10.1109/IRPS.2014.6861189
[7.] Saliva M., Cacho F., Ndiaye C., Huard V., Angot D., Bravaix A., Anghel L., "Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology," IEEE International Reliability Physics Symposium (IRPS), pp. CA.4.1 - CA.4.6, 2015.
Doi: 10.1109/IRPS.2015.7112782
[8.] Bravaix A., Saliva M., Cacho F., Federspiel X., Ndiaye C., Mhira S., Kussener E., Pauly E. Huard V., "Hot-Carrier and BTI Damage Distinction for High Performance Digital Application in 28nm FDSOI and 28nm LP CMOS nodes," IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), (San Feliu) pp.78-82, 2016.
Doi: 10.1109/IOLTS.2016.7604669
[9.] Bravaix A., Mhira S., Huard V., "FDSOI CMOS Technologies: New Resilient Digital Circuits Based on Adaptive Voltage Scaling for IoT Devices hardened against Variability and Aging," BIT's 7th Annual World Congress of nano Science & Technology, p. 32; 2017.
Best paper and Tutorial
[10.] Saliva M., Cacho F., Huard V., Federspiel X., Angot D., Benhassain A., Bravaix A., Anghel L., "Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI," Best Paper of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 441 - 446, 2015.
Doi: 10.7873/DATE.2015.0238
[11.] Bravaix A., "Hot-Carrier to Cold-Carrier Issues in nanoscale CMOS nodes: from Energy Driven to Multiple Particle regime," IEEE International Reliability Physics Symposium, Tutorial, Hyatt Regency Monterey Resort, USA, Sunday june 01 (Hawaii), 2014.
