Description
Electronic systems in cars and airplanes are becoming increasingly sophisticated and require more integration and performance. However, the use of highly integrated technologies compromises the reliability, safety and lifetime of the systems. New design approaches and solutions are needed that take into account this need for reliability.
The RESIST project targets these design methods as well as real-time adaptation methods for the next generation of ruggedized, resilient and adaptive electronic systems for automotive, avionics and aerospace in particular. RESIST focuses on the reliability, resilience, cost and quality of semiconductor-based circuits.
Objectifs
ISEN has participated in the design and testing of self-adaptive digital circuits by incorporating reliability criteria on the use of 40nm to 28nm CMOS (Si-bulk) and 28nm FDSOI technologies.
- Lifetimes in excess of 25 years for embedded systems
- 20% more component integration for the same level of reliability
- Testing costs less than 30%.
- Development of an alert system by monitoring the health of the systems
Main partner of the project
Partners
Main teacher-researchers involved
Project Director
Alain BRAVAIX
Activity manager
Doctoral students :
- Souhir Mhira (CIFRE ST Crolles)
- Marine Saliva (CIFRE ST Crolles)
More details
The CATRENE-RESIST project focused on the static and dynamic management of the electrical reliability of CMOS circuits (M40, LP28 and 28FD) under real conditions of use for applications with strong environmental constraints (Automotive, Avionics and Space).
The continuity of the integration of integrated circuits faces many challenges both at the level of their manufacture (fineness of the engraving) and the local and global variability of the devices at the nanometric scale which generate a significant dispersion of the electrical responses. It has therefore become essential in recent years to design a new, more robust generation of self-adapting CMOS circuits, dedicated to applications with higher constraints (voltage, temperature, power) such as automotive, avionics and space.
Transistors and circuits are subject to the trade-off between speed (performance), power consumption (low to very low) and aging (Aging) in operation, which become very difficult to reconcile for a mission/application profile aiming at a product lifetime. ISEN has been involved for the last 20 years in the incorporation of reliability in the hierarchy ("bottom-up") of circuit design, based on the main mechanisms of degradation responsible for wear and failure (progressive or sudden) of products.
These can be treated, as the different variability factors (PVT)to (circuits out of foundry) which impact the performance of the circuits, through aging at high temperature under negative bias, by hot carrier injections, and from the breakdown of the ultra-thin gate dielectrics in the transistors. This results in a progressive temporal variability that increases the rate of occurrence of errors at the circuit and system level, which must be managed at the hardware and software level in order to avoid the reduction of performance and then the failure (total or partial) of the circuit [1-5]. The principle is to follow as closely as possible the real conditions of use (V, T) using in-situ monitors, temperature sensors and error correction blocks, controlled by learning algorithm loops (and data storage), in order to apply a voltage compensation (VDD,VB) in static and dynamic mode (real time) to reduce the error density according to the activity rate (load,ton/toff), the required power level and the temperature. This allows to guarantee the correct operation in frequency for the maintenance of a power level, and finally to extend significantly the life of the circuit (product). This work has enabled the validation of the first 28nm Si-Bulk and 28nm FDSOI products from ST Microelectronics for real-time self-adaptive optimization of circuits dedicated to automotive applications.
Results obtained
ISEN has worked on the deployment of electrical test methodologies on nanometric transistors of M40, LP28 and 28FD technologies, digital cells and elementary CMOS circuits as well as on the supervision of the work of doctoral students Souhir Mhira and Marine Saliva. The main objective was to reinforce the robustness of the circuits subjected to strong environmental constraints (T, V, I, P) in operation. The protocols of monitoring/storing of parameters and the methodology of anticipation of aging (predictive modeling, window of detection of delays in critical paths) have allowed the development of algorithms of self-adaptation (dynamic management) in compromise performance in speed vs. consumption facing the aging of circuits(Fig.A1), to ensure their life in dynamic operation. The study allowed to realize a complete chain of validation by process, design and tests, which allows despite the process variability (dispersion of electrical responses due to the manufacturing steps at the nanometer scale), to compensate in real time the progressive drift of these criteria (aging) and to extend the lifetime of the circuits for applications with strong constraints such as automotive [3-7].
Fig.A2 : (a) Mesure de la loi de distribution de la différence de la tension de fonctionnement par rapport à la cible d’un processeur AR53 (1GHz), translatée par le gain apporté par la compensation effectuée par le générateur de tension en body bias (BBcomp) et par la compensation du vieillissement en temps réel, ce qui porte à 23% l’amélioration en vitesse sur processeur AR53 [14]. (b) La méthodologie permet d’atteindre 74% d’amélioration en énergie en combinant la compensation par l’effet body bias, la variabilité to (PVT) et la compensation du viellissement, montrant de meilleures performances en gain d’énergie en comparaison aux génération FinFETs (FF) de dernières générations, tout en garantissant une excellente robustesse ( < 1 ppm) et la sécurité pour l’utilisation automobile [11-14].
Several prototypes have allowed the methodology to evolve on the demonstrator with, at the beginning, the choice of in-situ monitors (on M40), the DC adaptation of the performances on the process variability (28LP), then the dynamic management of the three criteria mentioned above (FD28) which on this technology has been developed on the final demonstrator of the RESIST project(Fig.A2), to validate the self-adaptation technique at the system level (SoC) of the IPs in operation [11-14], using the ABB (Adaptive Body Bias) type adaptation which in the FDSOI technology, operates on transistors driven in double control gate with a compensation margin more important than for the bulk silicon technologies
Publications over the period
The results have been valorized by international publications at IRPS, ESREF, ITC, DATE, WCNS and tutorials (IRPS, ESREF) as well as articles in the journal Microelectronics Reliability. They have led the scientific and industrial community to a growing interest in these new types of CMOS self-adaptive circuits (28FD), premonitory of the current focus on the incorporation of AI at the system level, by allowing the validation of more robust circuits for automotive, avionics and aerospace applications. This work was awarded an Outstanding paper + 1 Best paper (IRPS 2017), a Best Paper (ITC India), and then an invited paper (ITC-USA). (list below)
Newspapers
[1.] A . Bravaix, , F. Cacho, X. Federspiel, C. Ndiaye, S. Mhira, V. Huard, "Potentiality of Healing Techniques in Hot-Carrier Damaged 28nm FDSOI CMOS nodes", Microelectronics Reliab., Vol.64, pp.163-167, Sept. 2016.
doi.org /10.1016/j.microrel.2016.07.092
[2.] V . Huard, S. Mhira, A. Bravaix, F. Cacho, "Enabling robust automotive electronic components in advanced CMOS nodes," Microelectronics Reliab., Vol. 76-77, pp. 13-24, 2017.
doi.org/10.1016/j.microrel.2017.07.064
IEEE International Conferences
[3.] Saliva M., Cacho F., Ndiaye C., Huard V., Angot D., Bravaix A., Anghel L., "Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology," IEEE International Reliability Physics Symposium (IRPS), pp. CA.4.1 - CA.4.6, 2015.
Doi: 10.1109/IRPS.2015.7112782
[4.] Saliva M., Cacho F., Huard V., Federspiel X., Angot D., Benhassain A., Bravaix A., Anghel L., "Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI",
Best Paper of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 441 - 446, 2015.
Doi: 10.7873/DATE.2015.0238
[5.] Mhira S., Huard V., Jain A., Cacho F., Meyer D., Naudet S., Bravaix A., Parthasarathy C., "Mission Profile Recorder: An Aging Monitor for Hard Events," IEEE International Reliability Physics Symposium (IRPS), 4C3-1 to 4C3-5, 2016.
Doi: 10.1109/IRPS.2016.7574539
[6.] Mhira S., Huard V., Cacho F., Benhassain A., Jain A., Parthasarathy C., Naudet S., Bravaix A., "Dynamic Adaptive Voltage Scaling in Automotive environment," Outstanding Paper of IEEE International Reliability Physics Symposium (IRPS), 3A-4.1 3A-4.7, 2017.
Doi: 10.1109/IRPS.2017.7936279
[7.] Sivadasan A., Mhira S., Notin A., Benhassain A., Huard V., Maurin E., Cacho F., Anghel L., Bravaix A., "Architecture- and Workload- Dependent Digital Failure Rate," IEEE International Reliability Physics Symposium (IRPS), CR-8.1 CR-8.4, 2017.
Doi: 10.1109/IRPS.2017.7936357
[8] Mhira S., Huard V., Cacho F., Benhassain A., Jain A. , Parthasarathy C., Naudet S., Bravaix A., "Dynamic aging compensation and Safety measures in Automotive environment" , IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), (Thessaloniki), pp. 1-7, 2017.
Doi: 10.1109/IOLTS.2017.8046204
[9.] Bravaix A., Mhira S., Huard V., "FDSOI CMOS Technologies: New Resilient Digital Circuits Based on Adaptive Voltage Scaling for IoT Devices hardened against Variability and Aging," BIT's 7th Annual World Congress of nano Science & Technology, p. 32; 2017.
[10.] Mhira S., Huard V., Bravaix A., Benhassain A., Cacho F., Naudet S., Jain A., Parthasarathy C., "Cognitive approach to support dynamic aging compensation", Best Paper of International Tests Conference, Bangalore (India), pp. 1-7, 2017.
Doi: 10.1109/TEST.2017.8242042
[11.] Huard V., Mhira S., A. Bravaix, De Tomasi M., Trabace E., Enrici Vaion R., Zabberoni P., "Robust Automotive Products in Advanced CMOS Nodes" , Best Paper of IEEE International Reliability Physics Symposium (IRPS), 3A-2.1 3A-2.7, 2017.
Doi: 10.1109/IRPS.2017.7936277
[12.] Huard V., Mhira S., Barclais A., Lecocq X., Raugi F., Cantournet M., Bravaix A., "Managing electrical reliability in consumer systems for improved energy efficiency" , in IEEE International Reliability Physics Symposium, (IRPS), 3C.1-1 3C.1-7, 2018.
Doi: 10.1109/IRPS.2018.8353561
[13] Mhira S., Huard V., Arora D., Flatresse P., Bravaix A., "Resilient Automotive Products through Process, Temperature and Aging Compensation Schemes," in IEEE International Reliability Physics Symposium, (IRPS), 3D.1-1, 3D.1-7, 2018.
Doi: 10.1109/IRPS.2018.8353568
[14.] Huard V., Ndiaye C., Arabi M., Parihar N., Federspiel X., Mhira S., Mahapatra S., Bravaix A., "Key Parameters Driving Transistor Degradation in Advanced Strained SiGe Channels," in IEEE International Reliability Physics Symposium, (IRPS), P-TX.4-1, P-TX.4-6, 2018.
Doi: 10.1109/IRPS.2018.8353699
Best paper and invited papers
[15.] Bravaix A., Cacho F., Ndiaye C., Federspiel X., Mhira S., Huard V., "BTI and HC coupled damage in 28nm to 14nm FDSOI CMOS nodes", Invited paper in Workshop on Dielectrics in Microelectronics (WoDIM), pp.38-39, (Catania), 2016.
[16.] Huard V., Mhira S., Cacho F., Bravaix A., "Enabling robust automotive electronic components in advanced CMOS nodes", presented as a keynote in ESREF opening (Bordeaux), 2017.
[17.] Mhira S., Huard V., Bravaix A., Benhassain A., Cacho F., Naudet S., Jain A., Parthasarathy C., "Cognitive approach to support dynamic aging compensation", Best Paper of International Tests Conference, Bangalore, India, presented as invited paper at ITC-Dallas, 2017.
Book and Chapter
"Hot Carrier Degradation in Semiconductor Devices"
Edition: SPRINGER, Editor: Tibor GRASSER; ISBN: 978-3-319-08993-5., pp. 1 -245, 2015.
Doi:10.1007/978-3-319-08994-2
Bravaix A., Huard V., Cacho F., Federspiel X., Roy D.
" Hot-Carrier Degradation in Decananometer CMOS nodes: from an energy driven to a unified current degradation modeling by multiple carrier degradation process", in Hot-Carrier degradation in Semiconductors, Springer ISBN 978-3-319-08993-5, Ed. T. Grasser, Chapter 3, pp. 57-103, 2015.
Doi: 10.1007/978-3-319-08994-2-2
