In the circuit development chain, particular attention must be paid to the reliability behavior of MOS devices as building blocks for advanced CMOS circuits during the development of a technology. At the device level, the behavior of the different degradation mechanisms are characterized. In contrast, in the final prototype, the product is characterized under accelerated aging conditions, but only macroscopic parameters can be extracted. One of the objectives of this thesis was to make the link between the reliability behavior of a circuit or system and its elementary bricks. The second important point was to develop 'smart' test solutions to improve the testability and space saving of the structures, to highlight the monitoring of the aging of the circuits and the compensation of the degradations. Another family of solutions consisted in reproducing directly in the structure the real excitation or configuration seen by the devices or elementary circuits during their life of use (lab in situ).

This thesis, carried out at STMicroelectronics (Crolles), is divided into five chapters, with the aim of progressively integrating device reliability into digital circuits: the first chapter presents the technological evolutions required to move from standard CMOS technologies (40LP, 28LP) to FDSOI technology for the 28nm node, as well as monotonic degradation mechanisms such as Bias Temperature Instability (BTI) and hot carrier injection (HCI). The second chapter deals with the phenomena of soft and hard gate oxide breakdown (TDDB) in MOS transistors, addressing the physical mechanisms, their localization, the associated statistical distributions, studying the different electrical models of breakdown and developing a compact model. The third chapter analyzes the impact of BTI and HCI degradation mechanisms in dedicated circuits such as ring oscillators, buffers and standard logic gate paths for different AC/DC, activity, high-temperature conditions and for two 28nm LP and FDSOI technologies. The fourth chapter focuses on the study of gate oxide breakdown in 8×8 ring oscillator (RO) arrays and circuits (ISCAS 432, ...) composed of logic gates, where the occurrence and impact of soft breakdown are investigated, comparing these different examples of circuits subjected to constant voltage stress or voltage ramps. Finally, Chapter 5 develops in-situ monitors for real-time monitoring of the reliability of circuits under BTI and HCI stress, which induce temporal and process-induced variability, considering the results obtained in the previous chapters on circuits subjected to BTI, HCI and breakdown degradation.