The integration of high-k dielectrics in transistor gate stacks has given rise to complex reliability issues. In addition, in view of sub-32nm planar technologies, new issues are arising from the use of completely FDSOI-free silicon-on-insulator substrates. Indeed, the integration of an oxide buried under the silicon film will not only modify the electrostatics of the structure but also introduce a new Si/SiO2 interface subject to possible degradation. This manuscript presents different electrical characterization methods as well as different reliability studies of FDSOI devices integrating High-κ/metal gate stacks. First, a complete study of the electrostatic coupling in FDSOI structures is performed, allowing to better understand the effect of a backside voltage on the electrical characteristics of the devices. Different methods of characterization of interface traps are then presented and adapted, when possible, to the specific case of FDSOI, where defects between the silicon film and the buried oxide must be taken into account. Finally, different reliability studies are presented, from PBTI and NBTI phenomena on long-channel devices to phenomena specific to small devices, such as the impact of hot carriers in ultra-thin film FDSOI structures and the parasitic effects of threshold voltage increase when transistor widths decrease.