The program consists in the development of advanced integrated circuit tests from current FDSOI CMOS digital nodes (28 to 22nm, operating at low voltage (LV) with VDD= 0.65 to 1V) to EDMOS extended drain BiCMOS mixed-signal circuits (from intermediate voltage (MV) to high voltage (HV), VDD = 10 to 20V) to study the reliability and robustness of the integrated circuit devices. The first goal will be to determine the main degradation mechanisms such as hot carrier injection, temperature instability under negative/positive bias (NBTI/PBTI) and breakdown of soft gate dielectric (SBD) and hard gate dielectric (HBD) that reduce the lifetime of devices and circuits for digital to analog applications, by developing accelerated lifetime techniques. Worst-case conditions are studied between global/local degradations and permanent/recoverable proportions of defects that will be studied in devices, cells and circuits, based on the most relevant parameters. Attention is given to a research axis based on the decoupling between temperature acceleration factors such as self-heating, thermal runaway aspects for LV and MV digital nodes as well as in mixed technologies operating in MV and HV. Another research axis is to distinguish the interaction mechanisms between natural irradiation and HC degradation with the objective of accurately modeling the worst-case damage according to device families, as well as their impacts in circuits subjected to high environmental stresses. The design and conception of test patterns for these topics will be developed during the thesis. The last aspect to be developed will be the use of Random Telegraph Noise (RTN) and 1/f measurement techniques applied to analog operation for fine fault analysis. The dedicated markets are the automotive applications and the Internet of Things (IoT).