The aim of this thesis is to study the process variability of recent CMOS technologies by designing new in-situ monitors to monitor and control the process variability of 40nm gate-length technologies dedicated to automotive applications (M40). The first stage consisted in determining the state of the art of the various achievements within STMicroelectronics' Process Monitoring Block (PMB) teams, in order to identify the parameters directly and indirectly linked to process variability that were not yet systematically taken into account. A design phase enabled us to create and incorporate PMBs for the logic and on-board memory (NVM) parts, included in a new microcontroller-based test chip. The IPs - Internet (Layer) Protocol - blocks enable measurement of the process variability of High Threshold Voltage (HVT) transistors using ring oscillators made up of standard cells (inverters, NAND, NOR) for the logic part. Different blocks will be proposed to establish the process variability over characteristic operating times. Four standard-cell ring oscillators have been implemented, enabling us to measure the impact of variability on oscillation frequencies, supply voltages, critical paths of logic blocks, measurement of non-volatile memory read access times, and measurement of "hybrid" critical paths (memory read access + logic). We are awaiting the Tape Out of these circuits. The final part will focus on extending this principle of using in-situ monitors to control temporal variability in real-time operation, to establish the impact of drifts due to aging of circuits (logic and NVM memory) with the impact of temperature.