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Lab' Micro & nano electronics

Nano2022_Prober

The micro & nano electronics laboratory

The laboratory's microelectronics activities began in 1994 at ISEN Yncréa Méditerranée with the arrival of A. Bravaix on the reliability of CMOS dies with D. Goguenheim, then with E. Kussener and H. Barthelemy on integrated circuit design. In 2000, the ISEN laboratory was involved in the creation of the L2MP (UMR 6137) with the University of Marseille, under the direction of M. Lannoo, ISEN's Director of Research. It was during this period that the first theses, supervised by Didier and Alain, were launched. In 2008, the L2MP/TECSEN merger led to the creation of IM2NP under the direction of R. Bouchakour as a joint research unit (UMR 6242) through the association of CNRS, Université Paul Cézanne Aix-Marseille III, Université de Provence andUniversité du Sud Toulon-Var , as well as three engineering schools:Ecole Polytechnique Universitaire de Marseille,Ecole Centrale de Marseille and ISEN Yncréa Méditerranée. Since 2017, the laboratory has been directed by Mr. Jean-Luc Autran as UMR 7334 between AMU and UTV, who is likewise director of the joint laboratory with ST Microelectronics the "Radiation Effect and Electrical Reliability" joint laboratory (REER), of which A. Bravaix is in charge of the Electrical Reliability section.

Doctoral students are supervised by ISEN Yncréa Méditerranée's research professors, who hold HDR (Habilitation to Supervise Research) degrees, and are hosted in ISEN Yncréa Méditerranée's laboratories or in the laboratories of local industrialists in the case of CIFRE theses.

The research work developed by the micro and nanoelectronics activity is carried out within the framework of contracts financed by regional, national and, in some cases, international industrialists (RESIST, IPCEI), as well as within the framework of collaborative partnerships resulting from the Competitiveness Clusters.

Microelectronics - Analog/Digital Design

A. Bravaix, H. Pitard (PhD student ISEN-IPCEI), T. Garba Seybou (PhD student CIFRE ST Crolles), G. Hamparsoumian (PhD student CIFRE ST Rousset)

The laboratory is focused on measurement and electrical test benches on components in boxes (A16442B), on devices, digital cells and elementary circuits on wafer from foundry (prober 300 and 200 mm). Accelerated stress methodologies (voltage, current, AC/DC cycles) allow to extract the lifetime of devices and circuits according to mission and temperature cycling profiles.

Theme

Study of semiconductor materials, dielectrics and metal contacts, reliability of components in endurance and performance.
Optimization of processes for the manufacture of CMOS and BiCMOS dies between the low voltage of cores and IO (low power) and high voltage (smart power)
Determination of lifetimes for transistors, cells, digital and analog circuits, NVM memories (EEPROM)

Achievements

1994-1995 BULL S.A. contrat direct – Fiabilité porteurs chauds de la technologie CMOS du du Lot W14 BB 5942 14 WAG 1, (J521, H5L1) LG= 0.5µm. 1995-1996 Projet Européen JESSI AE82 – Fiabilité et vieillissement AC/DC des technologies CMOS LG= 0.5-0.35 µm (J522 et J620 XLM, J643 EGK – Jupiter). 1996-1998 Projet régional CREMSI (Ia) – ST Rousset, N° 26: Caractérisation des oxydes interpoly dans les mémoires EPROM/EEPROM Projet régional CREMSI (Ib) – ATMEL ES2, N°18 Reliability Improvements for devices designed from CMOS node 0.35µm and below 1998-2000 Projet régional CREMSI (II) – ST Rousset N°14 : Fast Technique for Reliability Analysis of submicrometer CMOS (LATID vs. LDD). 1996-1997 Contrat Fiabilité avec ST Microelectronics (Crolles), filière H5 LDD CMOS avec LG= 0.5µm (VDD= 5V), Dégradation porteurs chauds en fonction du champ latéral. 1997-1998 Contrat Fiabilité avec ST Microelectronics (Crolles) filière H6 LDD CMOS avec LG= 0.35µm (VDD= 3.3V), ionisation primaire et secondaire (VB) en AC/DC. 1998-1999 Contrat Fiabilité avec ST Microelectronics (Crolles) pour la filière H7 LDD CMOS LG= 0.25µm (VDD=2.5V), Dégradation porteurs chauds DC et AC TPass. 1999-2000 Contrat Fiabilité avec ST Microelectronics (Crolles), filière H8 LDD CMOS avec LG= 0.18µm (VDD=1.8V), Dégradation porteurs chauds Wafer – J938YBB-16F7 ionisation primaire et secondaire (VB) en AC/DC. 2000-2001 Contrat Fiabilité avec ST Microelectronics (Crolles) filière H9 LDD CMOS avec LG= 0.18µm (VDD=1.8V), J938YBB-16F7 ionisation primaire et secondaire. 2001-2002 Contrat Fiabilité avec ST Microelectronics (Crolles) comparaison des filières 0.25-130nm CMOS et entre les dispositifs Low-Leakage (LL) et High-Speed (HS). 2002-2003 Contrat Fiabilité avec ST Microelectronics (Crolles) dégradation HC des filières NMOS 130nm, optimisation du champ latéral – J138FHD6. 2003-2004 Contrat Fiabilité avec ST Microelectronics (Crolles) pour la filière MDD 130nm dégradation HC dans le GO1-GO2 PMOS – wafer J203YB2 07A0 2004-2005 Contrat Fiabilité avec ST Microelectronics (Crolles), Dégradation porteurs chauds des MOSFETs canal N et P 130nm, dans le lot H9L1 wafer J203YB2 07A6. 2005-2006 Contrat Fiabilité avec ST Microelectronics (Crolles) pour la filière MDD 90nm CMOS comparaison de la dégradation NBTI et PBTI et effets de relaxation. 2006-2007 Contrat Fiabilité avec ST Microelectronics (Crolles) pour la filière MDD 90 nm N-Channel MOSFET’s – J138FHD62007- Effets des protections de grille 2007-2008 Contrat Fiabilité avec ST Microelectronics (Crolles) pour la filière MDD 65 nm N-Channel MOSFET’s – J138FHD62007- Durée de vie AC/DC. 2008-2009 Contrat Fiabilité avec ST Microelectronics (Crolles) Comparaison de la dégradation porteurs chauds et NBTI des filières 90nm et 65nm dispositifs GP vs. LP. 2009-2010 Contrat Fiabilité avec ST Microelectronics (Crolles) pour les filières CMOS C40 LG= 40nm (Q703GFZ), durée de vie en mode Off et modèle thermique HC-NBTI. 2010-2011 Contrat Fiabilité avec ST Microelectronics (Crolles) pour les filières C40 et 28nm FDSOI, modèle de durée de vie complet en énergie On/Off et sous mode AC. 2011-2012 Contrat Fiabilité avec ST Microelectronics (Crolles) pour les filières C28 et 28FD, à grille HKMG, dégradation NBTI et sous mode AC. 2012-2013 Contrat Fiabilité avec ST Microelectronics (Crolles) pour les filières 28FD et LP 24nm à grille HKMG, effet de VB (FWD/REV) sur la dégradation porteurs chauds. 2013-2014 Contrat Fiabilité avec ST Microelectronics (Crolles) pour les filières C28, effet de la largeur WG sur la dégradation NMOS et PMOS en AC/DC. 2014-2015 Contrat Fiabilité avec ST Microelectronics (Crolles) pour les filières FDSOI 28nm à 14nm, Optimisation de l’empilement de grille entre les lots Q340 et Q240 NMOS. 2006-2007 Projet CONTA avec Thalès-Avionics (Valence), Mesures TBS de la contamination de diélectrique mince dans les capteurs de pression/température. 2007-2008 Projet ARTHEMIS CIM-Conta, caractérisation électrique de l’influence des contaminants organiques et inorganiques sur les performances électriques des circuits. 2008-2009 Projet Focalisé avec ST Microelectronics (Rousset) sur la fiabilité des technologies CMOS avancées. 2009-2010 Projet COMET (FUI) avec la DGCIS sur la caractérisation électrique de l’impact des contaminants métalliques dans les technologies CMOS. 2009-2011 Projet NEXSAFE avec la société Nexess, le CEA, ID3 sur l’analyse de la fiabilité des technologies RFID utilisées sous forts rayonnements ionisants pour anticiper et renforcer par la conception des systèmes (balises et badges) en centrale nucléaire. 2013-2014 Contrat EADS (Suresnes) Fiabilité des technologies CMOS pour les applications Avioniques. 2014-2018 Projet Européen (CATRENE) RESIST sur la conception et le test de circuits numériques auto-adaptatifs pour contrôler la variabilité process des dispositifs à l’échelle nanométrique, les performances en fréquence et la consommation, puis le vieillissement en temps réel et à haute température, des circuits numériques CMOS. 2018-2022 Projet Nano 2022 IPCEI (1) avec ST Microelectronics (Crolles) sur l’optimisation et le vieillissement des technologies Low Power basse tension (CMOS) et smart power haute tension (LDMOS) pour les applications automotive

Defended PhDs

Framing A. Bravaix (15)
  1. Mickael DENAIS (09-11-2005), defended at the University of Marseille I

"Study of Negative Bias Temperature Instability (NBTI) in Submicron MOS Transistors of Advanced CMOS Stations 

  1. Chittoor PARTHASARATHY (09-10-2006.), defended at the University of Marseille I

"Studying the Reliability of Advanced CMOS Technologies: Application to Design Reliability Simulation of Digital and Analog Circuits".

  1. Thierry DiGILIO (20-10-2006), defended at the University of Marseille I

"Study of the Hot Carrier Reliability and Performance of 0.13µm - 2nm CMOS Technologies".

  1. Damien LACHENAL (13-11-2007), defended at INPG (Grenoble - Phelma)

"Study of Degradation Mechanisms of High Voltage MOS Transistors of Advanced CMOS and BiCMOS Technologies".

  1. Adrien ILLE (16-06-2008.), defended at the University of Marseille I

"Reliability of Ultra-thin Grid Oxides under Electrostatic Discharge (ESD) in Highly Submicron CMOS Technologies".

  1. Chloé GUERIN (10-10-2008), defended at INPG (Grenoble)

"Study of Hot Carrier Degradation of Advanced CMOS Technologies in Static and Dynamic Operation".

  1. Florence BELLENGER (29-11-2010), defended at IMEC (Belgium)

"Investigation of the Electrical properties of Ge / High-K gate Stack".

  1. Florian MOLIERE (25-11-2011), defended at the University of Marseille I

"Reliability of Highly Submicron Technologies (DSM) for Avionics, Space and Military Applications".

  1. Laurent BRUNET (08-03-2012), defended at INPG (Grenoble - Phelma).

"Electrical Characterization and Reliability of Transistors Integrating High-k Dielectrics and Metal Gates for Sub-32nm FDSOI Technologies".

  1. Yoann MAMY RANDRIAMIHAJA (02-11-2012), at INPG (Grenoble-Phelma)

"Reliability Study of Advanced CMOS Technologies from Fault Creation to Transistor and Circuit Degradation".

  1. Damien ANGOT (05-12-2014), defended at INPG (Grenoble-Phelma).

"Reliability and Temporal Variability of FDSOI-28nm CMOS Technologies, from Transistor to Integrated Circuit".

  1. Wafa ARFAOUI (24-09-2015), defended at INPG (Grenoble-Phelma)

"Hot Carrier Reliability (HCI) of 28nm High-K Metal Gate FDSOI Transistors".

  1. Marine SALIVA (02-10-2015.), defended at INPG (Grenoble-Phelma)

"Circuits dedicated to the study of Aging Mechanisms in advanced CMOS technologies: Design and measurements".

  1. Cheikh NDIAYE (07-07-2017), defended at INPG (Grenoble-Phelma)

"Study of Negative Bias Temperature Instability (NBTI) and Hot Carrier (HC) Reliability in 28nm and 14nm FDSOI CMOS".

  1. Souhir MHIRA (13-04-2018.), defended at INPG (Grenoble-Phelma)

"Innovative Methods for Static and Dynamic Management of the Electrical Reliability of CMOS M40 and 28FD Circuits under Real-life Conditions (HTOL)".

Framing D. Goguenheim (8)
  1. Céline TRAPES (16-01-2004), defended at the University of Marseille I

« Etude expérimentale des phénomènes de dégradation sous différents modes d’injection dans les oxydes ultra-minces (< 5nm) pour la microélectronique »

  1. David PIC (03-05-2007), defended at the University of Marseille I

Study of SiO2 oxide reliability in advanced CMOS devices and non-volatile memories

  1. Christelle BENARD (11-10-2008), defended at the University of Marseille I

"Studies of degradation phenomena in hot carrier MOS transistors and Negative-Bias Temperature Instability (NBTI) 

  1. Grégory DELAFOSSE (16-12-2011), defended at the University of Marseille I

"Self-assembly of C60 fullerenes on NH2-functionalized silicon oxide and gold surfaces"

  1. Sabrine TLILI (17-07-2012), defended at Aix Marseille University

"Study of the kinetics and equilibria of adsorption of volatile and semi-volatile organic compounds present in the atmosphere of clean rooms on microelectronic components during manufacturing" 

  1. Sophie d'AMBROSIO (26-06-2013), defended at Aix Marseille University

"Exchange interactions in the dilute magnetic semiconductor ZnO.Co"

  1. Marion CARMONA (04-03-2015), defended at Aix Marseille University

"Reliability of MOS transistors in embedded non-volatile memory technologies"

  1. Shiyu QIN (02-02-2016), defended at Aix Marseille University

"Electrical effect of metal contaminants in advanced microelectronic devices"

Material

  • 4 automated measurement and aging benches:
    1 probe station 12″(300mm), 2 probe stations 8″ (200mm), 1 probe station 5″ (127mm)
  • Parametric analyzers (2x) HP4145, (x1) 4155B, (x2) 4156C and fast measurement B1500-B1530 WGFMU (1µs-1ms) Low Power
  • B1525 high voltage measurement HV-SPGU (±40V, 400mA) for smart power
  • Measurements in Agilent 16442B box and wafer under tips (Karl-Suss)
  • I(V), C(V), G(V) 20Hz-1MHz, Charge-Pumping (2 and 3 pulses), AC Stress (2 and 3 pulses), Alternating DC, fast measurements (1µs - 1ms) with B1530 and 100µs (B1525)
  • DLTS (transient spectroscopy)
  • TDDB (Time-Dependent Dielectric Breakdown), NBTI (Negative Bias Temperature Instability), TBS (Thermal Bias Stress) measurements and Floating Grid technique
  • Temperature measurements T=77°K - 450°K / Baking at 300°C

Service offers

AC/DC reliability and wearout studies of CMOS dies under hot carriers (HC), temperature instability (NBT, PBT, TVS), breakdown of TDDB dielectrics (SILC, SBD, HBD). Experiments on wafer or in package.

AC-DC study on transistors, cells and elementary CMOS circuits

  • Technology optimization: process steps (doping, annealing, structure, design), mobility measurement, DC (VT, IOn/IOff, S, Gm/ID, PDC...) and AC (PAC, fosc, tcom...) parameters, quantum effect
  • Accelerated Lifetime Techniques (ALE) in DC/AC mode and temperature
  • Application of the Quasi-Static technique (10Hz - 15 Mhz)
  • Comparison of CMOS dies in Process/Performance/Robustness quality under AC/DC and temperature stress.
  • Characterization and measurement of defect quantities (NIT,Not, NHT and Nre relaxables)
  • Noise measurement in 1/f

Studies on the reliability of gille dielectrics,

  • Ultra thin to thick oxides (1.3nm to 20nm), High-K Metal gate dielectrics
  • Stress-Induced Leakage Currents (SILC), charging, antenna effect, flash EEPROMs (NOR, NAND)
  • Soft (SBD) and hard (HBD) breakdowns, statistical models (Poisson, Exponential, Normal and Log normal, Weibull and multimodal)

Microelectronics - Electrical reliability

E. Kussener, M. Teib (doctoral student CIFRE ST Rousset)

The research topic is to design analog and digital circuits that are of interest in the industry for low power, very low power, including multi-source energy recovery (piezoelectric, vibrational, photovoltaic and thermoelectric) for IoT and Big Data, for secure communication in contactless applications and the biomedical field.

Theme

  • Development of battery modules with energy recovery (BMS) of the multi-source type,
  • Circuit design with the development of low power analog solutions for power management in nano power mode (nano Watt technology) for microcontrollers
  • Development of very low power (ULP) measurement systems for real time environmental monitoring based on sensors (GPS, T, P, RH, RCO2, UV).
  • Circuits and embedded systems dedicated to medical applications.

Achievements

1998-1998 CG13 contract (Phases I and II) with ST Microelectronics (Rousset). NVM memories (Erevna), design of a secure ARM7 TDMI processor core with Flash memory.
2000-2000 MAGE project with ST Microelectronics (Rousset). Power interface, voltage reference, low consumption current and circuit security.
2003-2007 MEDEA contract with ATMEL on a new nanowatt design methodology dedicated to smard-card applications (CMOS 0.15µm).
2010-2011 CAPUCINE project - ANR. "Realization of a 6-axis sensor (3-axis accelerometer and 3-axis magnetometer called 3A3M) based on silicon nanowires."
2012 BIOP project Ministry of Defense. "Development of a portable prototype for collecting and analyzing cardiac data."
2011-2014 OSEO ProSECUR32 Competitiveness cluster project - IM2NP, "Secure Communicating Solutions on 32-bit processor."
2012-2015 DBS-PLASTICITY project - ANR, with IBDM, the EA 3845″Chronic deep brain stimulation of the subthalamic nucleus in rodent models of Parkinson's disease
2012-2015 MADNEMS project (LETI, IM2NP), with LETI, LVA, Neurelec and IM2NP on "Sensing by Electromechanical Gauge with Nano Silicon Lines (NEMS)".
2013-2016 NEWPASS as a CATRENE project with Gemalto, CEA-Leti, ID3 semiconductors, NXP and ST Microelectronics on the "Development of a technology platform for e-passport processing".

Defended PhDs

Framing E. Kussener (12)
  1. Vincent TELANDRO (23-11-2007), defended at the University of Marseille I

"Design of an integrated power system dedicated to smart card security".

  1. François RUDOLFF (25-11-2008), defended at the University of Marseille I

"Nanowatt Design Methodology dedicated to Smard-Card Applications". 

  1. Fabrice GUIGUES (29-11-2009), defended at the University of Marseille I

"Design of Nanowatt Analog Structures in Standard CMOS Technology".

  1. Anass SAMIR (21-01-2013), defended at the University of Marseille I

"Design of low power solutions and optimization of the energy management of systems dedicated to mixed applications.

  1. Florian BARRAU (16-12-2014), defended at the University of Marseille I

"Study of a localization solution in a wireless sensor network".

  1. Eric SAVARY (23-04-2015), defended at the University of Marseille I

"Design and integration of conditioning electronics for a silicon nanowire-based audio sensor"

  1. Julio AGUILAR (15-06-2015), defended at the University of Marseille I

"Design of a random value generator in CMOS AMS 0.35µm technology".

  1. Nicolas BOREL (03-12-2015), defended at the University of Marseille I

"Laser fault injection evaluation and countermeasure design on a low power architecture".

  1. Marc LACRUCHE (21-07-2016), defended at the University of Marseille I

"Security characterization of low power circuits against laser attacks 

  1. Benoit COURAUD (11-12-2017), defended at the University of Toulon

"Optimization of energy transfer for connected systems: application to RFID systems communicating in the near field at very high data rates".

  1. Elie COURDOUAN (17-12-2019), defended at the University of Toulon

 "Development of a multi-source harvesting BMS module

  1. Manon FOURNIOL (17-12-2020), defended at the University of Toulon

"Embedded processing of sensor signals for acoustic wake-up systems and magneto-inertial motion capture devices"

Material

  • Design assistance software: CADENCE chains, HSPICE (models)
  • Analog Artist - ELDO (analog) / Verilog-XL,
  • SYNARIO (digital, VHDL, FPGA),
  • Model Sim-VHDL, Leonardo Spectrum, NC Sim, FPGA (Digital),
  • MATLAB, PROTEL Channel,
  • Low-power CMOS analog/digital circuits: low-voltage amplifier, fast CMOS RC oscillator, DC/DC converter, 13.56MHz RF demodulator,
  • Cryptography: Integration of security algorithms or systems

Service offers

  • Design of analog/digital circuits ULP-LP, low frequency, ...
  • Power Interface for Smard-Cards and Biomedical Applications
  • STM32 programming - XCUBE.
  • Simulation under Cadence environment.

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