This thesis deals with the design and testing of the first self-adaptive nanometric CMOS circuits dedicated to automotive, avionics and aerospace applications, under highly constrained environments as they are subject to the trade-off between speed (performance), power consumption (Low Power) and aging (Aging). Different variability factors (PVT) that impact circuit performance have been studied as well as high-temperature aging under negative bias (NBT), hot-carrier aging (HCD), and breakdown of gate dielectrics (SBD), which result in a progressive temporal variability that increases the rate of error occurrence at the circuit and system level. Error density profiles as a function of activity rate and workload were first studied using static compensation techniques (S-AVS). The incorporation of in-situ monitors was performed by simulations and compared to measurements on silicon, which allowed to adapt in real time the trade-off in frequency, power consumption and error rate variation, which was not efficient enough in a static way, due to the limitations of the usage margins. This led us to lay the foundations for dynamic performance and aging management through a self-adaptive methodology (PVTA) developed throughout the design chain.

Innovative solutions were therefore developed with dynamic control loops to optimize the consumption of the various elements (design level) and blocks (system), while guaranteeing their proper functioning. The validation of the solutions was obtained step by step in the design chain, focusing first on the development of a first demonstrator in 40nm CMOS technology (M40) for STMicroelectronics' automotive applications. Different ways of error anticipation have been compared and the IS2M delay detection (with adjustable time windows) in critical paths has been selected as the most efficient one for the optimization solutions, which have been refined according to the usage profiles (Slow, Typical and Fast) and the multi-core loads. Theoretical modeling of the control loops led to a simulation tool based on Discrete Time Markov Chains (DTMC). This model was successfully compared with silicon measurements showing that the selected solutions offered a gain of reduction of the power consumed by 2 for equal performance and reliability.

In the last part, the high-level hierarchical modeling was applied on several systems/products of 28nm FDSOI CMOS nodes (28FD), in order to validate the relevance of the dynamic adaptation (D-ABB) in supply voltages and backside (VDD, VB) as well as the prediction based on the aging obtained on these systems/products under real time HTOL tests. This allowed to demonstrate the validity of the complete methodology by achieving accurate statistical prediction of reliability integrating the whole value chain in performance-consumption using advanced simulations, comparing to silicon data obtained under real conditions on boards. These longer term tests have allowed to refine the selection of the best D-ABB approaches of reliability by integrating the aspects of monitors, process variability, software suite, and by extending to the use of statistical learning algorithms (machine learning) with short and long term memory management. This work has enabled the validation of the first FDSOI products (28FD) of ST Microelectronics for a real-time self-adaptive optimization of these circuits dedicated to high stress applications.