In the industrial race for miniaturization and with the increasing technological demands for more performance on less area, the reliability of MOSFETs has become an increasingly complex subject of study. In order to maintain a continuous pace of miniaturization, new MOS transistor architectures have been introduced, conventional bulk silicon technologies are replaced by innovative technologies that improve electrostatic integrity such as FDSOI technology with high constant dielectric and metal gate. Despite all the innovations made on the MOS architecture, the degradation mechanisms remain more and more pronounced with the technological evolution. One of the most critical mechanisms of the advanced technologies is the hot-carrier-induced degradation (HCI) mechanism, indeed, the transition from one technological node to another is carried out at almost constant supply voltage. This induces an increase of the lateral field in the transistor which increases the risk of HCI degradation.

In order to guarantee the required performances while preserving the reliability of the devices, it is necessary to characterize and model the various failure mechanisms at the level of the elementary transistor. This thesis work focuses specifically on the hot carrier degradation mechanisms of 28nm FDSOI transistors which are compared to Bias Temperature Instability (BTI) mechanisms.

Based on the carrier energy, the voltage model proposed in this manuscript predicts the HC degradation by taking into account the substrate bias dependence (VB) including the effects of length L, gate oxide thickness TOX as well as BOX (TBox) and silicon film thickness TSI.

This work opens the way to the implementation of the HCI model for circuit simulators, which represents an important step to anticipate the reliability of future technology nodes and to verify the logic functionality of a circuit before proceeding to the design stages.