The microelectronics industry is trying to continue the race for miniaturization in order to meet Moore's law, by the realization of new transistor architectures proposed to replace the technology on silicon substrate (Si-bulk), because this one does not allow any more to continue the reduction of the scale factors until channel lengths of 10nm. For this reason, the Fully Depleted Silicon on Insulator (FDSOI) architecture was developed to improve transistor performance and continue the reduction of transistor dimensions below 20nm. The advantage of this architecture compared to the Si-bulk architecture is that it has a backside that can be used as a second gate to modulate the threshold voltage Vth of the transistor. We have tested in terms of performance and reliability two 28nm and 14nm CMOS nodes of FDSOI structures developed by STMicroelectronics. To improve the performance of p-channel transistors (PMOS), Germanium is introduced in the channel (SiGe) and in the source/drain for the 14nm FDSOI technology. Moreover, the reduction of the transistor geometry to these nanometric dimensions brings out physical design effects that impact both the performance and the reliability of the transistors.
This research work is developed in four chapters, the main topic of which is the performance and reliability of the latest CMOS generations subjected to BTI (Bias Temperature Instability) and hot carrier injection (HCI) degradation mechanisms in the latest 28nm and 14nm FDSOI technologies. In chapter I, we focus on the evolution of the transistor architecture that allowed the transition from 130-40nm low-power nodes on silicon substrate to FDSOI technology (28nm and 14nm). In Chapter II, the BTI and HCI degradation mechanisms of 28nm and 14nm FDSOI technologies are studied and compared with the standard models used. The impact of the physical design effects (Layout) on the electrical parameters and the reliability of the transistor are treated in chapter III by modeling the constraints induced by the introduction of SiGe. Finally, the aging and the degradation of the frequency performance have been studied in elementary circuits of ring oscillators (ROs) type, which is the subject of chapter IV. A new method to compensate the degradation in FDSOI transistors has been proposed using backside biasing (VB) to improve the lifetime of the transistors in the circuit in order to strongly improve the performance-reliability trade-off of digital circuits of nanometer length.