VHDL + Project

cours-elec

Semester

Level

Language

Specialization

ECTS

Prerequisites

Combinatorial and sequential logic.

Learning outcomes

At the end of this course, students will be able to:
- Implement the VHDL part of coding for synthesis.
- identify the differences between behavioral and structural coding styles
- distinguish between coding for synthesis and coding for simulation
- Use concurrent and sequential control structures to regulate information flow.
- Simulate a basic VHDL design
- Write a VHDL testbench and identify simulation-only constructs.

Course content

This course is an introduction to the VHDL language. Emphasis is placed on writing solid, synthesizable code and sufficient simulation to write a viable testbench. Structural and register transfer (RTL) coding styles are covered.
The software we used was ModelSim XE, the most useful simulation software in the industry.
+
At the end of this course and project, students will be able to:
- Implement the VHDL part of coding for synthesis.
- identify the differences between behavioral and structural coding styles
- distinguish between coding for synthesis and coding for simulation
- Use concurrent and sequential control structures to regulate information flow.
- Simulate a basic VHDL design
- Write a VHDL testbench and identify simulation-only constructs.
only.

Assessment method

Evaluation by teaching / Practical work

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